The present invention relates to a method for forming a storage node of a capacitor in a semiconductor device; and, more particularly, to a method for forming a storage node of a capacitor in a dynamic random access memory device.
As semiconductor devices have become highly integrated, the overall unit cell size has gradually decreased. For example, in a dynamic random access memory (DRAM) device, the unit cell comprises one transistor and one capacitor. Thus, as the integration scale of semiconductor devices has increased, it has become more difficult to control related processes.
FIGS. 1A to 1C relate to a method for forming a storage node of a capacitor in a DRAM device.
Referring to FIG. 1A, an inter-layer insulation layer 11 is formed on a substrate 10, where the inter-layer insulation layer 11 is patterned through a photolithography process to form a plurality of contact holes (not shown). An insulation layer and a polysilicon layer are sequentially formed inside each contact hole, and a chemical mechanical polishing (CMP) process is performed on the polysilicon layer and the insulation layer, thereby forming spacers 12 on sidewalls of the contact holes and a plurality of storage-node contact plugs 13 filled into the contact holes. A nitride layer 14, an oxide layer 15 and a hard mask layer 16 are sequentially formed on the above resulting substrate structure.
Referring to FIG. 1B, although not illustrated, a photoresist layer is formed on the hard mask layer 16, and a photo-exposure and developing process is performed with use of a mask, thereby forming a photoresist pattern. Then, the hard mask layer 16 is etched by using the photoresist pattern as an etch mask. After the etching of the hard mask layer 16, a hard mask pattern 16A is formed. The oxide layer 15 is then etched by using the hard mask pattern 16A as an etch barrier and this etching is stopped at the nitride layer 14. It should be appreciated that the nitride layer 14 acts as an etch stop layer. After the etching of the oxide layer 15, a plurality of first contact holes 17 exposing the nitride layer 14 are formed.
Referring to FIG. 1C, the nitride layer 14 is etched to form a plurality of second contact holes 17A exposing the storage-node contact plugs 13. Although not illustrated, a storage node layer, a dielectric layer and an upper electrode layer are sequentially formed over the second contact holes 17A and then, a CMP process is performed thereon, thereby forming capacitors.
However, as shown in FIG. 1C, there may be an incidence of misalignment between the second contact holes 17A and the storage-node contact plugs 13. Thus, when the nitride layer 14 is etched, the spacers 12 are also etched, thereby generating crevices A at sidewalls of the inter-layer insulation layer 11. Afterwards, when the storage node layer, the dielectric layer and the upper electrode layer are formed, a step coverage characteristic of the storage node layer becomes poor at the regions where the crevices A are generated. Therefore, leakage current of the capacitors increases, thereby causing defects in semiconductor devices.